PIC16F876A-I/ML【PDF 31/234 页】IC MCU FLASH 8KX14 A/D 28QFN

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PIC16F87XA

DS39582B-page 124

2003 Microchip Technology Inc.

FIGURE 10-11:

SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

10.4

USART Synchronous Slave Mode

Synchronous Slave mode differs from the Master mode

in the fact that the shift clock is supplied externally at

the RC6/TX/CK pin (instead of being supplied internally

in Master mode). This allows the device to transfer or

receive data while in Sleep mode. Slave mode is

entered by clearing bit, CSRC (TXSTA<7>).

10.4.1

USART SYNCHRONOUS SLAVE

TRANSMIT

The operation of the Synchronous Master and Slave

modes is identical, except in the case of the Sleep mode.

If two words are written to the TXREG and then the

SLEEP

instruction is executed, the following will occur:

The first word will immediately transfer to the

TSR register and transmit.

The second word will remain in TXREG register.

Flag bit TXIF will not be set.

When the first word has been shifted out of TSR,

the TXREG register will transfer the second word

to the TSR and flag bit TXIF will now be set.

If enable bit TXIE is set, the interrupt will wake

the chip from Sleep and if the global interrupt is

enabled, the program will branch to the interrupt

vector (0004h).

When setting up a Synchronous Slave Transmission,

follow these steps:

Enable the synchronous slave serial port by set-

ting bits SYNC and SPEN and clearing bit

CSRC.

Clear bits CREN and SREN.

If interrupts are desired, then set enable bit

TXIE.

If 9-bit transmission is desired, then set bit TX9.

Enable the transmission by setting enable bit

TXEN.

If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

Start transmission by loading data to the TXREG

If using interrupts, ensure that GIE and PEIE

(bits 7 and 6) of the INTCON register are set.

CREN bit

RC7/RX/DT

RC6/TX/CK

Write to

bit SREN

SREN bit

RCIF bit

(Interrupt)

Read

RXREG

Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRG = 0.

Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

‘0’

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

‘0’

Q1 Q2 Q3 Q4

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